1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a memory device and a system including the same.
2. Description of the Related Art
A memory device stores data inputted from the outside, and outputs the stored data to the outside. The memory device includes a plurality of data buses formed therein, through which data are transmitted. The data buses include a global data bus and a local data bus. The global data bus serves to transmit data between a data input/output pad and memory banks and is shared by the memory banks. The local data bus is provided for each of the memory banks.
FIG. 1 is a block diagram illustrating a conventional memory device.
First, in a write operation, data inputted through a data pad DQ is loaded onto a global data bus GIO through a receiver 102. Then, the data is transferred to the vicinities of memory banks 110 and 120. When the memory bank 110 is selected, the data of the global data bus GIO is loaded onto local data bus pair LIO_B0 and LIOb_B0 of the memory bank 110 by a write driver (WTDRV) 112. Then, the data loaded in the local data bus pair LIO_B0 and LIOb_B0 is written to a memory cell selected in the memory bank 110. When the memory bank 120 is selected, the data of the global data bus GIO is loaded onto local data bus pair LIO_B1 and LIOb_B1 of the memory bank 120 by a write driver 122, and written to a memory cell selected in the memory bank 120.
Second, in a read operation, when the memory bank 110 is selected, data stored in a memory cell selected in the memory bank 110 is loaded onto the local data bus pair LIO_B0 and BIOb_B0, amplified by an I/O sense amplifier (IOSA) 111, and loaded onto the global data bus GIO. Then, the data transferred to the vicinities of the data pad DQ by the global data bus GIO is outputted to the outside of the memory device by a transmitter 101. When the memory bank 120 is selected, data stored in a memory cell selected in the memory bank 120 is outputted to the outside of the memory device through the local data bus pair LIO_B1 and LIOb_B1, an I/O sense amplifier 121, the global data bus GIO, and the transmitter 101.
FIG. 2 is a diagram for explaining a concern occurring when a read operation is successively performed on the same memory cell, in the conventional memory device shown in FIG. 1. In FIG. 2, it is assumed that an active and read operation is performed for one word line and one bit line.
Referring to FIG. 2, a word line WL is activated in response to an active command at a time point 201. When the word line WL is activated, data of a memory cell corresponding to the word line WL is loaded onto a bit line pair BL and BLb. Referring to FIG. 2, it can be seen that the level of a bit line BL becomes higher than the level of a complementary bit line BLb by charge sharing between the memory cell and the bit line pair BL and BLb. At a time point 202, a bit line sense amplifier is enabled, and a slight potential difference between the bit line pair BL and BLb is amplified by the bit line sense amplifier. Then, the bit line BL has a level corresponding to a core voltage VCORE, which is a high-level voltage used in a cell area, and the complementary bit line BLb has a level corresponding to a ground voltage VSS, which is a low-level voltage used in the cell area.
Time points 203, 204, and 205 indicate sections in which read operations are performed by read commands. During the sections in which the read operations are performed, the voltage levels of the bit line BL and the complementary bit line BLb are transferred to the local data bus pair LIO and LIOb. That is, the local data bus pair LIO and LIOb is driven by the bit line pair BL and BLb. Thus, the voltage level of the bit line BL momentarily decreases, and the voltage level of the complementary bit One BLb momentarily increases. The voltage levels of the bit line BL and the complementary bit One BLb, which are momentarily decreased and increased, are recovered to the original levels by the bit line sense amplifier. When the read operations 203, 204, and 205 are successively performed as illustrated in FIG. 2, the voltage levels of the bit line pair BL and BLb may not be completely recovered, but a voltage difference between the bit line pair BL and BLb may gradually decrease. Then, as indicated by reference numeral 206, the voltage difference between the bit line BL and the complementary bit line BLb may decrease to cause a fail in which the voltage levels of the bit line and the complementary bit line are changed to each other.
During the operation of the memory device, successive read operations on the same memory cell may occur frequently. Thus, a technique capable of preventing a fail caused by successive read operations on the same memory cell is in demand.